Ming-Yu Liu 48 publications . Priyanka Raina. View Rangharajan Venkatesan's profile on LinkedIn, the world's largest professional community. Previous methods that train DNNs in low-precision typically keep a . The field of interest covered includes: Rangharajan Venkatesan: NVIDIA: Ravi Rajwar: Google: Ravishankar Iyer: Intel: Rene Mueller: Huawei Zurich Research Center, Switzerland: Resit Sendag: University of Rhode Island: Ronald Dreslinski: University of Michigan: Rui Hou: Institute of Information Engineering, Chinese Academy of Sciences: Rujia Wang: Illinois Institute of Technology . Rangharajan Venkatesan, Yakun Sophia Shao, Miaorong Wang, Jason Clemons, Steve Dai, Matthew Fo-jtik, Ben Keller, Alicia Klinelter, Nathaniel Pinckney, Yanqing Zhang, Brian Zimmer, William J. Dally, Joel S. Emer, Stephen W. Keckler, Brucek Khailany International Conference on Computer Aided Design (ICCAD), November 2019 He is currently pursuing the Ph.D. degree with the School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA. Yanqing Zhang. Articles Cited by Public access Co-authors. Authors: Steve Dai, Rangharajan Venkatesan, Haoxing Ren, Brian Zimmer, William J. Dally, Brucek Khailany. SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks Angshuman Parashar Minsoo Rhu Anurag Mukkara Antonio Puglielli Rangharajan Venkatesan Brucek Khailany Joel Emer Stephen W. Keckler William J. Dally NVIDIA Massachusetts Institute of Technology UC-Berkeley Stanford University . B Zimmer, R Venkatesan, YS Shao, J Clemons, M Fojtik, N Jiang, B Keller, . Crafting an effective statement of purpose March 16, 2021; SOP Sample From Khorana Alum February 19, 2021; The Covid-19 Research: How India Responds? 2. How to say Rangharajan Venkatesan in English? (8/1) We have had a very successful event! Aritra Dhar. Quantization maps floating-point weights and activations in a . Puglielli, Rangharajan Venkatesan, Brucek Khailany, Joel Emer, Stephen W. Keckler, and William J. Dally. Rangharajan Venkatesan, Yakun Sophia Shao, Brian Zimmer, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina . Recent News. Timeloop uses a concise and unified representation of the key . Yang Hu. Download PDF Abstract: Quantization enables efficient acceleration of deep neural networks by reducing model memory footprint and exploiting low-cost integer math hardware units. ACM is meeting this challenge, continuing to work to improve the automated merges by tweaking the weighting of the evidence in light of experience. (7/31) The electronic proceedings is also accessible online when you login as user "ISLPED2012" with the Wi-Fi passport as handed out at the symposium. Title. Fax: 205-921-5595 2131 Military Street S Hamilton, AL 35570 View Location Joel S. Emer Thomas Gray. 2017. Rangharajan Venkatesan NVIDIA Santa Clara, CA, USA rangharajanv@nvidia.com Ben Keller NVIDIA Santa Clara, CA, USA benk@nvidia.com Brucek Khailany NVIDIA Austin, TX, USA bkhailany@nvidia.com AbstractHigh-level synthesis (HLS) has recently been used to improve design productivity for many units in today's complex SoCs. A 6T SRAM design at a sub-10-nm node calls for carefully designed transistors so that new leakage mechanisms, such as direct source-to-drain . Crafting an effective statement of purpose March 16, 2021; SOP Sample From Khorana Alum February 19, 2021; The Covid-19 Research: How India Responds? This hardware-software synergy leads to an elegant exten-sion of current accelerator architectures for implementing per-vector scaling with low overhead. Senior Research Scientist, NVIDIA. ACM/IEEE Design Automation Conference (DAC), June 2018 . Most frequent co-Author . Tensorloop is an infrastructure for evaluating and exploring the architecture design space of deep neural network (DNN) accelerators. Rangharajan_CV : Last Updated: 04/28/2014 00:36:49 Manage this page Manage your menu Zope help documents . Sponsored by IEEE and SSCS, the International Solid-State Circuits Conference - ISSCC - is the foremost global forum for presentation of advances in solid-state circuits and systems-on-a-chip. Jason Clemons. [13] Rainer Storn and Kenneth Price. Rangharajan Venkatesan's 20 research works with 1,158 citations and 2,239 reads, including: Low-Precision Training in Logarithmic Number System using Multiplicative Weight Update Full text data coming soon. Jie-Fang Zhang, Ching-En Lee, Chester Liu, Yakun Sophia Shao. Rangharajan Venkatesan. Domain wall memory (DWM) is a recently developed spin-based memory technology in . In ISPASS. Rangharajan Venkatesan 5 publications . He received the B.Tech. 205-921-5556. 27-40. MAGNet: A Modular Accelerator Generator for Neural Networks Rangharajan Venkatesan, yYakun Sophia Shao, Miaorong Wang,zJason Clemons, Steve Dai, yMatthew Fojtik, Ben Keller, yAlicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Yanqing Zhang,yBrian Zimmer,y William J. Dally, yJoel Emer,yzStephen W. Keckler, Brucek Khailanyy NVIDIAy Massachusetts Institute of Technologyz Stanford University Matthew Fojtik. See the complete profile on LinkedIn and discover . Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen G Tell, Yanqing Zhang, William J Dally, Joel S Emer, C Thomas Gray, Stephen W Keckler, Brucek Khailany Presenter Name: Institution: Title: ISCA'17. (7/27) The final program has been updated.. degree in electronics and communication engineering from Indian Institute of Technology, Roorkee, India, in 2009. dac 2019: 39 [doi] A 0.11 pJ/Op, .32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, Jason . Stephen G. Tell. Rui Hou. JUNE 2021 | VOL. Huawei Zurich Research Center, Switzerland. Rangharajan Venkatesan. Past JSSC Best Paper Award Winners Amrit Nagarajan 1 publication. Differential evolution-a simple and efcient heuristic for global optimization over continuous spaces. PRIMAL: Power Inference using Machine Learning Yuan Zhou, Haoxing Ren, Yanqing Zhang, Ben Keller, Brucek Khailany, Zhiru Zhang. Nan Jiang Ben Keller. Agendas April Mini-Workshop Monday, April 27. Minsoo Rhu . Figure 1 (a) shows a Simba package consisting of a 6x6 array of Simba chiplets connected via a mesh interconnect. 64 | NO. SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks Angshuman Parashar Minsoo Rhu Anurag Mukkara Antonio Puglielli Rangharajan Venkatesan Brucek Khailany Joel Emer Stephen W. Keckler William J. Dally NVIDIA Massachusetts Institute of Technology UC-Berkeley Stanford University aparashar@nvidia.com . Bibliometrics: In 1926, Alfred Lotka formulated his power law (known as Lotka's Law) describing the frequency of publication by authors in a given field. Find Rangharajan Venkatesan's accurate email address and contact/phone number in Adapt.io. Ali Javadi-Abhari. Rangharajan Venkatesan. 2017. Stephen W. Keckler Brucek Khailany . 6 | COMMUNICATIONS OF THE ACM 107 Simba: Scaling Deep-Learning Inference with Chiplet-Based Architecture By Yakun Sophia Shao, Jason Cemons, Rangharajan Venkatesan, Brian Zimmer, Matthew Fojtik, Nan Jiang, Ben Keller, Anima Anandkumar 121 publications . HP Enterprise Gen-Z Chipset. His research interests include variation-tolerant design . Jacob R Stevens, Rangharajan Venkatesan, Steve Dai, Brucek Khailany, and Anand Raghunathan. Two different spintronic memory technologies Domain Wall Memory (DWM) and STT-MRAM . Patrick Knebel of HP Enterprise presented their Gen-Z chipset. Scaling Equations for the Accurate Prediction of CMOS Device Performance from . Rangharajan Venkatesan. Currently working as Senior Research Scientist at NVIDIA in California, United States. University of Florida. This thesis makes the following contributions towards the design of computing platforms with spintronic devices. Search Search. B Keller, M Fojtik, B Khailany. The IEEE Circuits and Systems Society is the leading organization that promotes the advancement of the theory, analysis, computer-aided design and practical implementation of circuits, and the application of circuit theoretic techniques to systems and signal processing. TCAS-II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Pronunciation of Rangharajan Venkatesan with and more for Rangharajan Venkatesan. Authors: Jiawei Zhao, Steve Dai, Rangharajan Venkatesan, Ming-Yu Liu, Brucek Khailany, Bill Dally, Anima Anandkumar. People: Angshuman Parashar, Priyanka Raina, Sophia Shao, Rangharajan Venkatesan, Yu-Hsin Chen, Brucek Khailany, Stephen W. Keckler, Joel Emer. Spin-based devices have shown great potential in enabling high-density, energy-efficient memory and are therefore, considered highly promising for the design of future computing platforms. Xing Hu. Deep Learning Hardware Machine Learning for EDA Agile Hardware Design Methodology Spin Memories. Rangharajan has 7 jobs listed on their profile. Some photos can be found in the gallery link. Rangharajan Venkatesan is this you? Independent Consultant. newest | popular; Activity Feed; Likes; 0 research 03/19/2021. Angshuman Parashar, Priyanka Raina, Yakun Sophia Shao, Yu-Hsin Chen, Victor A. Ying, Anurag Mukkara, Rangharajan Venkatesan, Brucek Khailany, Stephen W. Keckler, Joel Emer March 2019 In ISPASS Timeloop: A Systematic Approach to DNN Accelerator Evaluation The Conference offers a unique opportunity for engineers working at the cutting edge of IC design and application to maintain technical currency, and to network with leading experts. William J. Dally. IEEE, 2017. , Stephen W. Keckler, Zhengya Zhang. PDF Code He has served as a member of the technical program committees of several leading IEEE conferences including International Solid-State Circuits Conference . The major contribu-tions of our work are as follows: We propose VS-Quant, a novel per-vector scaled quantiza- Search within Rangharajan Venkatesan's work. Each Simba chiplet, as shown in Figure 1 (b), contains an array of PEs, a global PE, a NoP router, and a controller, all connected . Nathaniel Pinckney. degree in Electronics and Communication Engineering from the Indian Institute of Technology, Roorkee in 2009 and the Ph.D. degree in Electrical and Computer Engineering from Purdue University in August 2014. 1) It explores the use of spintronic memories in the design of a domain-specific processor for an emerging class of data-intensive applications, namely recognition, mining and synthesis (RMS). WINStep Forward Promoting Science and Technology Between India and the U.S 2015 21st IEEE International Symposium on Asynchronous Circuits and Systems, 1-8, 2015. Softermax: Hardware/Software Co-Design of an Efficient Softmax for Transformers. Abstract. Sanchari Sen 4 publications . Download PDF Abstract: Representing deep neural networks (DNNs) in low-precision is a promising approach to enable efficient acceleration and memory reduction. Google Scholar; Aaron Stillmaker and Bevan Baas. Senior Research Scientist, NVIDIA - Cited by 2,296 - Deep Learning Hardware - Machine Learning for EDA - Agile Hardware Design Methodology - Spin Memories The 36-chiplet Simba system is functional over a slightly narrower voltage range, from 0.52 to 1.1 V, achieving 0.16 pJ/op at 0.52 V and 484 MHz; at 1.1 V, the 36-chiplet system achieves a 1.8 GHz PE frequency and 128 TOPS. Lukas Cavigelli. Recent News. Home Rangharajan Venkatesan. It is shown that the holistic device-circuit-architecture co-design enables all the levels in the cache hierarchy to be realized using DWM and benefit from its improved density, and proposes TapeCache, a DWM-based cache design that employs device, circuit, and architectural techniques to address these challenges. Mukkara, Rangharajan Venkatesan, Brucek Khailany, Stephen W. Keckler, Joel Emer International Symposium on Performance Analysis of Systems and Software (ISPASS), March 2019. Angshuman Parashar, Priyanka Raina, Yakun Sophia Shao, Yu-Hsin Chen, Victor A. Ying, Anurag Mukkara, Rangharajan Venkatesan, Brucek Khailany, Stephen W. Keckler, Joel Emer (2019). Yu Hua. Skip slideshow. Timeloop: A Systematic Approach to DNN Accelerator Evaluation. Rangharajan Venkatesan is a Senior Research Scientist in the ASIC & VLSI Research group in NVIDIA. Awards Two best-paper awards and four design-contest awards were given out at the banquet on July 31. mans;Venkatesan et al.,2019;NVIDIA Corporation,2020). HLS tools Brucek Khailany, Evgeni Krimer, Rangharajan Venkatesan, Jason Clemons, Joel Emer, Matthew Fojtik, Alicia Klinefelter, Michael Pellauer, Nathaniel Pinckney, Yakun Sophia Shao, Shreesha Srinath, Christopher Torng, Sam (Likun) Xi, Yanqing Zhang, Brian Zimmer. Alicia Klinefelter. Yu Hua. Yakun Sophia Shao is with the Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA 94720 USA. 2018 A Modular Digital VLSI Flow for High-Productivity SoC Design Brucek Khailany, Matthew Fojtik, Alicia Klinefelter, Evgeni Krimer, Michael Pellauer, Nathaniel Pinck- Domain-Specific Many-core Computing using Spin-based Memorymore. Rangharajan Venkatesan, Yakun Sophia Shao, Miaorong Wang, Jason Clemons, Steve Dai, Matthew Fojtik,Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina . Rangharajan Venkatesan received the B.Tech. This involves three chiplets that are built on the same reticle, but are then combined in different . Anand Raghunathan 18 publications . This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO). Angshuman Parashar, Minsoo Rhu, Anurag Mukkara, Antonio Puglielli, Rangharajan Venkatesan, Brucek Khailany, Joel Emer, Stephen W. Keckler, and William J. Dally. Jour- Venkatesan, Rangharajan has not filed any forms with the United States Securities and Exchange Commission. ii ACKNOWLEDGMENTS First and foremost, I would like to express my sincere gratitude to my advisor, 2021. Rangharajan Venkatesan vs Anjali Srikanth on 27 January, 2021. Rene Mueller. Brucek Khailany, Evgeni Krimer, Rangharajan Venkatesan, Jason Clemons, Joel S. Emer, Matthew Fojtik, Alicia Klinefelter, Michael Pellauer, Nathaniel Pinckney, Yakun Sophia Shao, Shreesha Srinath, Christopher Torng, Sam (Likun) Xi, Yanqing Zhang, and Brian Zimmer, "A modular digital VLSI flow for high-productivity SoC design," in Proceedings of . SNAP: An Efficient Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference. 0 followers Featured Co-authors. Steve Dai 4 publications . Rangharajan Venkatesan of NVIDIA presented their research project using network-on-chip (NoC) and network-on-package (NoP) chiplet integration strategy. There was strong difference of opinion between the petitioner/husband and the respondent/wife during their Marital . no code implementations 23 May 2017 Angshuman Parashar, Minsoo Rhu, Anurag Mukkara, Antonio Puglielli, Rangharajan Venkatesan, Brucek Khailany, Joel Emer, Stephen W. Keckler, William J. Dally Convolutional Neural Networks (CNNs) have emerged as a fundamental technology for machine learning. At 1.2 V, each chiplet operates with a 2 GHz PE frequency for a peak throughput of 4 TOPS. Rangharajan Venkatesan. by Rangharajan Venkatesan and Charles Augustine. William J. Dally 17 publications . Asymmetric Underlapped FinFETs for Near- and Super-Threshold Logic at Sub-10nm Technology Nodes A. ARUN GOUD, RANGHARAJAN VENKATESAN, ANAND RAGHUNATHAN, and KAUSHIK ROY, Purdue University, West Lafayette, Indiana Extending double-gate FinFET scaling to sub-10nm technology regime requires device-engineering techniques for countering the rise of direct source to drain tunneling (DSDT . Rangharajan_CV : Last Updated: 04/28/2014 00:36:49 Manage this page Manage your menu Zope help documents . 3.3. IEEE Journal of Solid-State Circuits (JSSC), February 2021. His research interests include machine learning accelerators, low-power VLSI design, and SoC design methodologies. Rangharajan Venkatesan. WINStep Forward Promoting Science and Technology Between India and the U.S Congratulations to#PurdueECE professors Anand Raghunathan and Kaushik Roy, and alumni Rangharajan Venkatesan and Amit Agrawal, winners of the ICCAD Liked by Zhewen Pan arXiv preprint arXiv:2103.09301. Brucek Khailany, Evgeni Krimer, Rangharajan Venkatesan, Jason Clemons, Joel S. Emer, Matthew Fojtik, Alicia Klinefelter, Michael Pellauer, Nathaniel Pinckney, Yakun Sophia Shao, Shreesha Srinath, Christopher Torng, Sam (Likun) Xi, Yanqing Zhang, and Brian Zimmer, "A modular digital VLSI flow for high-productivity SoC design," in Proceedings of . Huawei Technologies. Included is the whole spectrum from basic scientific theory to industrial applications. May 2014 Session: Rangharajan Venkatesan, Purdue University July 2014 Session: Shankar Ganesh Ramasubramanian, Purdue University November 2014 Session: Mihir Pendharkar, University of California - Santa Barbara. Ashish Ranjan, Swagath Venkataramani, Zoha Pajouhi, Rangharajan Venkatesan, more Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 > 356 - 361 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE) claim profile. Chinese Academy of Sciences, Institute of Computing Technology. Kaushik Roy. October 3, 2020; Sign Up to Receive Our Newsletter . 27: SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks. Rangharajan Venkatesan. However, its overall energy efficiency is limited by the energy requirements of spin-transfer torque switching during writes and reliable single-ended sensing during reads. Rangharajan Venkatesan is a Senior Research Scientist with NVIDIA. Biblio data only below the dashed line. "Scnn: An accelerator for compressed-sparse convolutional neural networks." In 2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA), pp. In Proceedings of the 44th Annual International Symposium on Computer Architecture (ISCA '17 . RANGHARAJAN VENKATESAN Graduate Research Fellow, Integrated Systems Laboratory, Email: rvenkate@purdue.edu School of Electrical and Computer Engineering, Purdue University Phone: (765) 491-5934 . GNNerator: A Hardware/Software Framework for Accelerating Graph Neural Networks . Brian Zimmer, Rangharajan Venkatesan, Ben Keller, Yanqing Zhang, and William J. Dally are with NVIDIA Corporation, Santa Clara, CA 94305 USA (e-mail: bzimmer@nvidia.com). October 3, 2020; Sign Up to Receive Our Newsletter . Angshuman Parashar, Minsoo Rhu, Anurag Mukkara, Antonio Puglielli, Rangharajan Venkatesan, Brucek Khailany, Joel Emer, Stephen W. Keckler, and William J. Dally. 28: 2020: A pausible bisynchronous FIFO for GALS systems. "Buffets: An Efficient and Composable Storage Idiom for Explicit Decoupled Data Orchestration", Michael Pellauer, Yakun Sophia Shao, Jason Clemons, Neal Crago, Kartik Hegde, Rangharajan Venkatesan, Stephen W Keckler, Christopher W. Fletcher, Joel Emer, International Conference on Architectural Support for Programming Languages and Operating . Anand Raghunathan. Invention Title: 2/3/2022: Nvidia Corporation: Assignee: Application Publication: 17530852 20220076110: Efficient Neural Network Accelerator Dataflows Rangharajan Venkatesan: NVIDIA: Ravi Rajwar: Google: Ravishankar Iyer: Intel: Rene Mueller: Huawei Zurich Research Center, Switzerland: Resit Sendag: University of Rhode Island: Ronald Dreslinski: University of Michigan: Rui Hou: Institute of Information Engineering, Chinese Academy of Sciences: Rujia Wang: Illinois Institute of Technology . Rangharajan Venkatesan, Amit Agarwal, Kaushik Roy, Anand Raghunathan (Purdue University) Ernest S. Kuh Early Career Award Jeyavijayan Rajendran (Texas A&M University) Figure 1 illustrates the three-level hierarchy of the Simba architecture: package, chiplet, and PE. Huazhong University of Science and Technology. Sort. Rangharajan Venkatesan In Partial Fulllment of the Requirements for the Degree of Doctor of Philosophy December 2014 Purdue University West Lafayette, Indiana. Date Recorded: Party: Role: Document Type: Document No. Scnn: An accelerator for compressed-sparse convolutional neural networks. Rangharajan Venkatesan: NVIDIA: Ravi Soundararajan: VMware: Reetuparna Das: University of Michigan: Resit Sendag: University of Rhode Island: Reza Hojabr: Simon Fraser University: Robert Bell: Samsung: Ronald Dreslinski: University of Michigan: Ruby Lee: Princeton: Rui Hou: Institute of Information Engineering, Chinese Academy of Sciences . Verified email at nvidia.com - Homepage. The case of the petitioner is that the petitioner has married the respondent on 04.12.2016 as per Hindu rites and Customs at Sri Sadari Bhavanam, Ahobilam, Tambaram. Rangharajan VENKATESAN has filed for patents to protect the following inventions. Nima Honarmand. Huawei Zurich Research Center. Angshuman Parashar, Minsoo Rhu, Anurag Mukkara, Antonio Puglielli, Rangharajan Venkatesan, Brucek Khailany, Joel S. Emer, Stephen W. Keckler, William J. Dally: ACM Transactions on Computer Systems, September 2015: Efficient Control and Communication Paradigms for Coarse-Grained Spatial Architectures IEEE Journal of Solid-State Circuits 55 (4), 920-932, 2020. Rangharajan Venkatesan: NVIDIA: Ravi Soundararajan: VMware: Reetuparna Das: University of Michigan: Resit Sendag: University of Rhode Island: Reza Hojabr: Simon Fraser University: Robert Bell: Samsung: Ronald Dreslinski: University of Michigan: Ruby Lee: Princeton: Rui Hou: Institute of Information Engineering, Chinese Academy of Sciences . Yakun Sophia Shao. STT-MRAM has attracted great interest for use as on-chip memory due to its high density, near-zero leakage and high endurance. Institute of Information Engineering, Chinese Academy of Sciences.